This invention relates to a switching stage of the Darlington type comprising a first transistor having a base, which constitutes the input of the stage, adapted to receive a control signal, whose voltage varies between a so-called selection level and a so-called non-selection level. The emitter of the first transistor acts upon the base of a second transistor whose emitter, which constitutes the output of the stage, is adapted to be connected to a first current source when the said logic control signal is at its selection level and to a second current source of lower intensity than the first source when the said logic control signal is at its non-selection level.
Such a switching stage is currently used as an output stage, i.e. one per line of a line decoder of a high-speed memory. The selected line is traversed by a considerable selection current and the other lines are traversed by a hold current which is markedly smaller.
During a loading of addresses at the input of the decoder corresponding to the selection of a different line, the current in the line, which is deselected, passes for a period designated as the deselection time from a high current level to a considerably lower level, and vice versa for a period designated as the selection time for the line which is selected, the other lines remaining at the same current level.
It is well known to those skilled in the art that the deselection time is longer than the selection time.
The memory access time is consequently especially determined by the capacitance of the output stages of the decoder in order to ensure that this current decrease is obtained in a minimum period of time.